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KAD5612P
General Description
Preliminary
Dual 12-Bit, 250/210/170/125MSPS A/D Converter
The KAD5612P is a family of low-power, highperformance, dual-channel 12-bit, analog-to-digital converters. Designed with Kenet's proprietary FemtoCharge(R) technology on a standard CMOS process, the family supports sampling rates of up to 250MSPS. The KAD5612P-25 is the fastest member of this pin-compatible family, which also features sample rates of 210MSPS (KAD5612P-21), 170MSPS (KAD5612P-17) and 125MSPS ( KAD5612P-12). A serial peripheral interface (SPI) port allows for extensive configurability, as well as fine control of gain, skew and offset matching between the two converter cores. Digital output data is presented in selectable LVDS or CMOS formats. The KAD5612P is available in a 72contact QFN package with an exposed paddle. Performance is specified over the full industrial temperature range (-40 to +85C).
CLKP CLKN CLKOUTP CLKOUTN
AINP AINN
VREF
D[11:0]P D[11:0]N ORP ORN OUTFMT OUTMODE
VREF
VCM
BINP BINN
1.25V
Features
* * * * * * * * * * * Programmable gain, offset and skew control 1.3 GHz analog input bandwidth 52fs Clock Jitter Over-range indicator Selectable Clock Divider: /1, /2 or /4 Clock Phase Selection Nap and Sleep modes Two's complement, Gray code or Binary data format DDR LVDS-compatible or LVCMOS outputs Programmable Built-in Test Patterns 1.8V Analog and Digital Supplies
Key Specifications
* * * SNR = 65.1dBFS for fIN = 124MHz (-1dBFS) SFDR = 81dBc for fIN = 124MHz (-1dBFS) Power consumption * 400mW @ 250MSPS * 312mW @ 125MSPS
Pin-Compatible Family
Model
KAD5612P-25 KAD5612P-21 KAD5612P-17 KAD5612P-12 KAD5610P-25 KAD5610P-21 KAD5610P-17 KAD5610P-12
Resolution
12 12 12 12 10 10 10 10
Speed (MSPS)
250 210 170 125 250 210 170 125
Applications
* * * * * * Power Amplifier Linearization Radar and Satellite Antenna Array Processing Broadband Communications High-Performance Data Acquisition Communications Test Equipment WiMAX and Microwave Receivers
300 Unicorn Park Dr., Woburn, MA 01801 Sales: 1-781-497-0060 FemtoCharge is a registered trademark of Kenet, Inc. Rev 0.5.1 Preliminary
Sales@kenetinc.com Copyright (c) 2007, Kenet, Inc. Page 1
KAD5612P
Table of Contents
Section
Electrical Specifications DC Specifications AC Specifications Digital Specifications Timing Diagrams Switching Specifications Absolute Maximum Ratings Thermal Impedance ESD Pinout/Package Information Pin Descriptions Pin Configuration Typical Performance Characteristics Theory of Operation Functional Description Power-On Calibration User-Initiated Reset Analog Input Clock Input Jitter Voltage Reference Digital Outputs Power Dissipation Nap/Sleep Data Format
Pages
3-7 3 4 5 5 6 6 7 7 8-9 8 9 10-13 14-18 14 14 15 15 16 16 16 17 17 17 18
Section
Serial Peripheral Interface SPI Physical Interface SPI Configuration DUT Information Indexed DUT Configuration/Control Global DUT Configuration/Control DUT Test SPI Memory Map Equivalent Circuits Layout Considerations Definitions Outline Dimensions Ordering Guide Revision History
Pages
18-24 19 20 21 21 22 23 24 25 25 26 27 28 28
Rev 0.5.1 Preliminary
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KAD5612P
Electrical Specifications
All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V, TA = -40C to +85C, AIN = -1dBFS, fSAMPLE = Maximum Conversion Rate (per speed grade).
DC Specifications
KAD5612P-25 Parameter Analog Input Full-Scale Analog Input Range Input Resistance Input Capacitance Full Scale Range Temp. Drift Input Offset Voltage Gain Error Common-Mode Output Voltage Power Requirements 1.8V Analog Supply Voltage 1.8V Digital Supply Voltage 1.8V Analog Supply Current 1.8V Digital Supply Current Power Supply Rejection Ratio Power Dissipation Normal Mode Nap Mode Sleep Mode PD PD PD 400 40 10 TBD TBD TBD 371 40 10 TBD TBD TBD 345 40 10 TBD TBD TBD 312 40 10 TBD TBD TBD mW mW mW AVDD OVDD IAVDD IOVDD PSRR 1.7 1.7 1.8 1.8 157 65.0 -53 1.9 1.9 TBD TBD 1.7 1.7 1.8 1.8 142 63.6 -53 1.9 1.9 TBD TBD 1.7 1.7 1.8 1.8 130 60.7 -53 1.9 1.9 TBD TBD 1.7 1.7 1.8 1.8 116 57.2 -53 1.9 1.9 TBD TBD V V mA mA dBFS VFS RIN CIN AVTC VOS EG VCM Differential Differential Differential Full Temp 1.38 1.45 1000 4 90 1.5 0.6 0.535 1.59 1.38 1.45 1000 4 90 1.5 0.6 0.535 1.59 1.38 1.45 1000 4 90 1.5 0.6 0.535 1.59 1.38 1.45 1000 4 90 1.5 0.6 0.535 1.59 VPP pF ppm/C mV % V Symbol Conditions Min Typ Max KAD5612P-21 Min Typ Max KAD5612P-17 Min Typ Max KAD5612P-12 Min Typ Max Units
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KAD5612P
AC Specifications
KAD5612P-25 Parameter Differential Nonlinearity Integral Nonlinearity Minimum Conversion Rate Maximum Conversion Rate Signal-to-Noise Ratio Symbol DNL INL fS MIN fS MAX SNR fIN = 10MHz fIN = 70MHz fIN = 140MHz fIN = 230MHz fIN = 400MHz fIN = 974MHz Signal-to-Noise and Distortion SINAD fIN = 10MHz fIN = 70MHz fIN = 140MHz fIN = 230MHz fIN = 400MHz fIN = 974MHz Effective Number of Bits ENOB fIN = 10MHz fIN = 70MHz fIN = 140MHz fIN = 230MHz fIN = 400MHz fIN = 974MHz Spurious-Free Dynamic Range SFDR fIN = 10MHz fIN = 70MHz fIN = 140MHz fIN = 230MHz fIN = 400MHz fIN = 974MHz Intermodulation Distortion IMD fIN = 10MHz fIN = 70MHz fIN = 170MHz Two-Tone SFDR 2TSFDR fIN = 10MHz fIN = 70MHz fIN = 170MHz Channel to Channel Isolation fIN = 10MHz fIN = 124MHz fIN = 170MHz Word Error Rate Full Power Bandwidth FPBW TBD TBD TBD TBD 250 65.2 65.1 65.1 64.8 64.2 61.4 64.0 64.0 63.7 63.5 62.2 53.9 10.3 10.3 10.3 10.3 10.0 8.7 84 84 79 77 71 57 TBD -90.5 -86.0 TBD TBD TBD 90 90 TBD 10-12 1.3 TBD TBD TBD TBD TBD TBD Conditions fIN = 10MHz fIN = 10MHz Min TBD TBD Typ Max TBD TBD TBD 210 65.8 65.7 65.6 65.7 TBD TBD 65.5 65.7 65.2 65.2 TBD TBD 10.6 10.6 10.5 10.5 TBD TBD 84 83 78 76 TBD TBD TBD TBD TBD TBD TBD TBD 90 90 TBD 10-12 1.3 TBD TBD TBD TBD TBD TBD KAD5612P-21 Min TBD TBD Typ Max TBD TBD TBD 170 66.2 66.2 66.0 66.1 TBD TBD 66.0 65.9 65.7 65.6 TBD TBD 10.7 10.7 10.6 10.6 TBD TBD 85 82 78 77 TBD TBD TBD TBD TBD TBD TBD TBD 90 90 TBD 10-12 1.3 TBD TBD TBD TBD TBD TBD KAD5612P-17 Min TBD TBD Typ Max TBD TBD TBD 125 66.7 66.6 66.4 66.3 TBD TBD 66.4 66.3 66.0 65.8 TBD TBD 10.7 10.7 10.7 10.6 TBD TBD 85 83 79 79 TBD TBD TBD TBD TBD TBD TBD TBD 90 90 TBD 10-12 1.3 GHz TBD TBD KAD5612P-12 Min TBD TBD Typ Max TBD TBD TBD Units LSB LSB MSPS MSPS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS dBFS Bits Bits Bits Bits Bits Bits dBc dBc dBc dBc dBc dBc dBFS dBFS dBFS dBc dBc dBc dB dB dB
Rev 0.5.1 Preliminary
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KAD5612P
Digital Specifications
Parameter
Inputs Input Current High (RESETN) Input Current Low (RESETN) Input Current High (OUTMODE, NAP/SLP, CLKDIV, OUTFMT ) Input Current Low (OUTMODE, NAP/SLP, CLKDIV, OUTFMT ) Input Capacitance LVDS Outputs Differential Output Voltage Output Offset Voltage Output Rise Time Output Fall Time CMOS Outputs Voltage Output High Voltage Output Low Output Rise Time Output Fall Time VOH VOL tR tF OVDD-0.1 0.1 TBD TBD V V ns ns VT VOS tR tF 210 TBD 500 500 mV mV ps ps IIH IIL IIH IIL CDI VIN = 1.8V VIN = 0V 0 25 TBD TBD 1 50 25 25 3 10 75 TBD TBD A A A A pF
Symbol
Conditions
Min
Typ
Max
Units
Timing Diagrams
Figure 1. LVDS Timing Diagram--DDR
Figure 2. CMOS Timing Diagram--DDR
Rev 0.5.1 Preliminary
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KAD5612P
Switching Specifications
Parameter
ADC Aperture Delay RMS Aperture Jitter Input Clock to Output Clock Propagation Delay Input Clock to Data Propagation Delay Output Clock to Data Propagation Delay Latency (Pipeline Delay) Over Voltage Recovery tA jA tCPD tPD tDC L tOVR TBD TBD TBD 375 52 TBD TBD TBD 7.5 1 TBD TBD TBD ps fs ps ps ps cycles cycles
Symbol
Min
Typ
Max
Units
Absolute Maximum Ratings1
Parameter
AVDD to AVSS OVDD to OVSS AVSS to OVSS Analog Inputs to AVSS Clock Inputs to AVSS Logic Input to AVSS Logic Inputs to OVSS Operating Temperature Storage Temperature Junction Temperature
Min
-0.4 -0.4 -0.3 -0.4 -0.4 -0.4 -0.4 -40 -65
Max
2.1 2.1 0.3 AVDD + 0.3 AVDD + 0.3 OVDD + 0.3 OVDD + 0.3 85 150 150
Units
V V V V V V V C C C
1. Exposing the device to levels in excess of the maximum ratings may cause permanent damage. Exposure to maximum conditions for extended periods may affect device reliability.
Rev 0.5.1 Preliminary
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KAD5612P
Thermal Impedance
Parameter
Junction to Paddle2 Junction to Case2 Junction to Ambient2
Symbol
JP JC JA
Typ
30 TBD TBD
Unit
C/W C/W C/W
2. Paddle soldered to ground plane.
ESD
Electrostatic charge accumulates on humans, tools and equipment and may discharge through any metallic package contacts (pins, balls, exposed paddle, etc.) of an integrated circuit. Industry-standard protection techniques have been utilized in the design of this product. However, reasonable care must be taken in the storage and handling of ESD sensitive products. Contact Kenet for the specific ESD sensitivity rating of this product.
Rev 0.5.1 Preliminary
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KAD5612P
Pin Descriptions
Pin #
1, 6, 19, 24, 71 2-5, 17, 18, 28-31 7, 10-12, 72 8, 9 13, 14 15 16 20, 21 22 23 25 26, 45, 55, 65 27, 36, 56 32, 33 34, 35 37, 38 39, 40 41, 42 43, 44 46 47, 48 49, 50 51, 52 53, 54 57, 58 59, 60 61, 62 63, 64 66 67 68 69 70 Exposed Paddle
LVDS [LVCMOS] Name
AVDD DNC AVSS BINP, BINN AINN, AINP VCM CLKDIV CLKP, CLKN OUTMODE NAPSLP RESETN OVSS OVDD D0N, D0P [NC, D0] D1N, D1P [NC, D1] D2N, D2P [NC, D2] D3N, D3P [NC, D3] D4N, D4P [NC, D4] D5N, D5P [NC, D5] RLVDS CLKOUTN, CLKOUTP [NC, CLKOUT] D6N, D6P [NC, D6] D7N, D7P [NC, D7] D8N, D8P [NC, D8] D9N, D9P [NC, D9] D10N, D10P [NC, D10] D11N, D11P [NC, D11] ORN, ORP [NC, OR] SDO CSB SCLK SDIO OUTFMT AVSS
LVDS [LVCMOS] Function
1.8V Analog Supply Do Not Connect Analog Ground B-Channel Analog Input Positive, Negative A-Channel Analog Input Negative, Positive Common Mode Output Clock Divider Control Clock Input True, Complement Output Mode (LVDS, LVCMOS) Power Control (Nap, Sleep modes) Power On Reset (Active Low) Output Ground 1.8V Output Supply LVDS Bit 0 (LSB) Output Complement, True [NC, LVCMOS Bit 0] LVDS Bit 1 Output Complement, True [NC, LVCMOS Bit 1] LVDS Bit 2 Output Complement, True [NC, LVCMOS Bit 2] LVDS Bit 3 Output Complement, True [NC, LVCMOS Bit 3] LVDS Bit 4 Output Complement, True [NC, LVCMOS Bit 4] LVDS Bit 5 Output Complement, True [NC, LVCMOS Bit 5] LVDS Bias Resistor (connect to OVSS with a 10k, 1% resistor) LVDS Clock Output Complement, True [NC, LVCMOS CLKOUT] LVDS Bit 6 Output Complement, True [NC, LVCMOS Bit 6] LVDS Bit 7 Output Complement, True [NC, LVCMOS Bit 7] LVDS Bit 8 Output Complement, True [NC, LVCMOS Bit 8] LVDS Bit 9 Output Complement, True [NC, LVCMOS Bit 9] LVDS Bit 10 Output Complement, True [NC, LVCMOS Bit 10] LVDS Bit 11(MSB) Output Complement, True [NC, LVCMOS Bit 11] LVDS Over Range Complement, True [NC, LVCMOS Over Range] SPI Serial Data Output (4.7k pull-up to OVDD is required) SPI Chip Select (active low) SPI Clock SPI Serial Data Input/Output Output Data Format (Two's Comp., Gray Code, Offset Binary) Analog Ground
LVCMOS Output Mode Functionality is shown in brackets (NC = No Connection) Rev 0.5.1 Preliminary Page 8
KAD5612P
Pin Configuration
AVDD DNC DNC DNC DNC AVDD AVSS BINP BINN AVSS AVSS AVSS AINN AINP VCM CLKDIV DNC DNC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37
AVSS AVDD OUTFMT SDIO SCLK CSB SDO OVSS ORP ORN D11P D11N D10P D10N D9P D9N OVDD OVSS
KAD5612
72 QFN
Top View Not to Scale
D8P D8N D7P D7N D6P D6N CLKOUTP CLKOUTN RLVDS OVSS D5P D5N D4P D4N D3P D3N D2P D2N
Rev 0.5.1 Preliminary
AVDD CLKP CLKN OUTMODE NAPSLP AVDD RESETN OVSS OVDD DNC DNC DNC DNC D0N D0P D1N D1P OVDD
19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
Figure 3. Pin Configuration
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KAD5612P
Typical Performance Curves
90.0 SNRFS (dBFS) & SFDR (dBc) 85.0 80.0 75.0 70.0 65.0 60.0 55.0 50.0 0 200 400 600 800 1000 INPUT FREQUENCY (MHz) SNRFS SFDR
TBD
Figure 4. SNR & SFDR vs. fIN
Figure 5. HD2 & HD3 vs. fIN
TBD
TBD
Figure 6. SNR & SFDR vs. AIN
Figure 7. HD2 & HD3 vs. AIN
TBD
TBD
Figure 8. SNR & SFDR vs. fSAMPLE
Figure 9. HD2 & HD3 vs. fSAMPLE
Rev 0.5.1 Preliminary
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KAD5612P
Typical Performance Curves
TBD
TBD
Figure 10. Power vs. fSAMPLE
Figure 11. Differential Nonlinearity
TBD
TBD
Figure 12. Integral Nonlinearity
Figure 13. SNR & SFDR vs. VCM
TBD
TBD
Figure 14. Noise Histogram
Figure 15. Single Tone Spectrum @ 10 MHz
Rev 0.5.1 Preliminary
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KAD5612P
Typical Performance Curves
TBD
TBD
Figure 16. Single Tone Spectrum @ 70 MHz
Figure 17. Single Tone Spectrum @ 140 MHz
TBD
TBD
Figure 18. Single Tone Spectrum @ 240 MHz
Figure 19. Single Tone Spectrum @ 500 MHz
TBD
TBD
Figure 20. Two-Tone Spectrum @ 10 MHz
Figure 21. Two-Tone Spectrum @ 70 MHz
Rev 0.5.1 Preliminary
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KAD5612P
Typical Performance Curves
TBD
TBD
Figure 22. Two-Tone Spectrum @ 140 MHz
90 SNRFS (dBFS) & SFDR (dBc) 85 80
Figure 23. Two-Tone Spectrum @ 240 MHz
SFDR 75 SNRFS 70 65 60 -40 -20 0 20 40 60 80 TEMPERATURE (C)
TBD
Figure 24. Two-Tone Spectrum @ 500 MHz
90 SNRFS (dBFS) & SFDR (dBc) 85 80 SFDR 75 SNRFS 70 65 60 1.6 1.65 1.7 1.75 1.8 1.85 1.9 1.95 2 AVDD & OVDD (V)
Figure 25. SNR & SFDR vs. Temperature
Figure 26. SNR & SFDR vs. Power Supply Voltage
Rev 0.5.1 Preliminary
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KAD5612P
Functional Description
The KAD5612P is based upon a 12-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (Figure 27). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge domain techniques are used to successively compare the input to a series of reference charges. Decisions made during the successive approximation operations determine the digital code for each input value. The converter pipeline requires six samples to produce a result. Digital error correction is also applied, resulting in a total latency of seven and a half clock cycles. This is evident to the user as a latency between the start of a conversion and the data being available on the digital outputs. The device contains two A/D converter cores with carefully matched transfer characteristics. At startup, each core performs a self-calibration to minimize gain and offset errors. The reset pin (RESETN) is initially set high at power-up and will remain in that state until the calibration is complete. The clock frequency should remain fixed during this time, and no SPI communications should be attempted. Recalibration can be initiated via the SPI port at any time after the initial self-calibration.
Power-On Calibration
At start-up, the core performs a self-calibration to minimize gain and offset errors. An internal power-onreset (POR) circuit detects the supply voltage ramps and initiates the calibration when the analog and digital supply voltages are above a threshold. The following conditions must be adhered to for the power-on calibration to execute successfully: A frequency-stable conversion clock must be applied to the CLKP/CLKN pins * DNC pins (especially 3, 4 and 18) must not be pulled up or down * SDO (pin 66) must be high * RESETN (pin 25) must begin low * SPI communications must not be attempted A user-initiated reset can subsequently be invoked in the event that the above conditions cannot be met at power-up. The SDO pin requires an external 4.7k pull-up to OVDD. If the SDO pin is pulled low externally during power-up, calibration will not be executed properly. After the power supply has stabilized the internal POR releases RESETN and an internal pull-up pulls it high, which starts the calibration sequence. The RESETN pin should be connected to an open-drain driver with a drive strength of less than 0.5mA. *
Figure 27. ADC Core Block Diagram Rev 0.5.1 Preliminary Page 14
KAD5612P
The calibration sequence is initiated on the rising edge of RESETN, as shown in Figure 28. The overrange output (OR) is set high once RESETN is pulled low, and remains in that state until calibration is complete. The OR output returns to normal operation at that time, so it's important that the analog input be within the converter's full-scale range in order to observe the transition. If the input is in an over-range condition the OR pin will stay high and it will not be possible to detect the end of the calibration cycle. While RESETN is low, the output clock (CLKOUTP/CLKOUTN) stops toggling and is set low. Normal operation of the output clock resumes at the next input clock edge (CLKP/CLKN) after RESETN is deasserted. At 250MSPS the nominal calibration time is 300ms.
Figure 29. Analog Input Range An RF transformer will give the best noise and distortion performance for wideband and/or high intermediate frequency (IF) inputs. Two different transformer input schemes are shown in Figures 30 and 31.
Figure 30. Transformer Input for General Purpose Applications Figure 28. Calibration Timing
User-Initiated Reset
Recalibration of the ADC can be initiated at any time by driving the RESETN pin low for a minimum of one clock cycle. An open-drain driver with a drive strength of less than 0.5mA is recommended. As is the case during power-on reset, the SDO, RESETN and DNC pins must be in the proper state for the calibration to successfully execute. Figure 31. Transmission-line Transformer Input for High IF Applications A back-to-back transformer scheme is used to improve common mode rejection, which keeps the common mode level of the input matched to VCM. The value of the shunt resistor should be determined based on the desired load impedance. The differential input resistance of the KAD5612P is 1000. The SHA design uses a switched capacitor input stage, which creates charge kick-back when the sampling capacitance is reconnected to the input voltage. This kick-back creates a disturbance at the input which must settle before the next sampling point. Lower source impedance will result in faster settling and improved performance. Therefore a 1:1 transformer and low shunt resistance are recommended for optimal performance.
Analog Input
Each ADC core contains a fully differential input (AINP/AINN, BINP/BINN) to the sample and hold amplifier (SHA). The ideal full-scale input voltage is 1.45V, centered at the VCM voltage of 0.535V as shown in Figure 29. Best performance is obtained when the analog inputs are driven differentially. The common mode output voltage, VCM, should be used to properly bias the inputs as shown in Figures 30 through 32. Rev 0.5.1 Preliminary
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KAD5612P
tails on this are contained in the Serial Peripheral Interface section. A delay-locked loop (DLL) generates internal clock signals for various stages within the charge pipeline. If the frequency of the input clock changes, the DLL may take up to 52s to regain lock at 250MSPS. The lock time is inversely proportional to the sample rate.
Jitter
Figure 32. Differential Amplifier Input A differential amplifier, as shown in Figure 32, can be used in applications that require dc-coupling. In this configuration the amplifier will typically dominate the achievable SNR and distortion performance. In a sampled data system, clock jitter directly impacts the achievable SNR performance. The theoretical relationship between clock jitter (tJ) and SNR is shown in Equation 1 and is illustrated in Figure 34.
Clock Input
The clock input circuit is a differential pair (see Figure 47). Driving these inputs with a high level (up to 1.8VPP on each input) sine or square wave will provide the lowest jitter performance. A transformer with 4:1 impedance ratio will provide increased drive levels. The recommended drive circuit is shown in Figure 33. The clock can be driven single-ended, but this will reduce the edge rate and may impact SNR performance. The clock inputs are internally self-biased to AVDD/2 to facilitate ac coupling.
SNR - dB
100 95 90 85 80 75 70 65 60 55 50 1
1 SNR = 20 log 10 2 f t IN J
Equation 1.

tj=0.1ps 14 Bits
tj=1ps
12 Bits
tj=10ps
10 Bits
tj=100ps
10
100
1000
Input Frequency - MHz
Figure 34. SNR vs. Clock Jitter This relationship shows the SNR that would be achieved if clock jitter were the only non-ideal factor. In reality, achievable SNR is limited by internal factors such as linearity, aperture jitter and thermal noise. Internal aperture jitter is the uncertainty in the sampling instant shown in Figure 1. The internal aperture jitter combines with the input clock jitter in a rootsum-square fashion, since they are not statistically correlated, and this determines the total jitter in the system. The total jitter, combined with other noise sources, then determines the achievable SNR.
Figure 33. Recommended Clock drive A selectable 2X/4X divider is provided in series with the clock input. The divider can be used in the 2X mode with a sample clock equal to twice the desired sample rate. This will result in a clock input with 50% duty cycle and will maximize the converter's performance.
CLKDIV Pin
AVSS Float AVDD
Divide Ratio
2 1 4
Voltage Reference
A temperature compensated voltage reference provides the reference charges used in the successive approximation operations. The full-scale range of each A/D is proportional to the reference voltage. The nominal value of the voltage reference is 1.25V. Page 16
Table 1. CLKDIV Pin Settings The clock divider can also be controlled through the SPI port, which overrides the CLKDIV pin setting. DeRev 0.5.1 Preliminary
KAD5612P
Digital Outputs
Output data is available as a parallel bus in LVDScompatible or CMOS modes. In either case, the data is presented in double data rate (DDR) format with the A and B channel data available on alternating clock edges. When CLKOUT is low channel A data is output, while on the high phase channel B data is presented. Figures 1 and 2 show the timing relationships for LVDS and CMOS modes, respectively. Additionally, the drive current for LVDS mode can be set to a nominal 3 mA or a power-saving 2 mA. The lower current setting can be used in designs where the receiver is in close physical proximity to the ADC. The applicability of this setting is dependent upon the PCB layout, therefore the user should experiment to determine if performance degradation is observed. The output mode and LVDS drive current are selected via the OUTMODE pin as shown in Table 2.
OUTMODE Pin
AVSS Float AVDD
TBD
Figure 35. Power vs. Sample Rate, LVDS Mode
TBD
Mode
LVCMOS LVDS, 3 mA LVDS, 2 mA
Table 2. OUTMODE Pin Settings The output mode can also be controlled through the SPI port, which overrides the OUTMODE pin setting. Details on this are contained in the Serial Peripheral Interface section. An external resistor creates the bias for the LVDS drivers. A 10k, 1% resistor must be connected from the RLVDS pin to OVSS.
Figure 36. Power vs. Sample Rate, CMOS Mode
Nap/Sleep
Portions of the device may be shut down to save power during times when operation of the ADC is not required. Two power saving modes are available: nap, and sleep. Nap mode reduces power dissipation to 40mW and recovers to normal operation in approximately 1s. Sleep mode reduces power dissipation to 10mW but requires 1ms to recover. The clock should remain running and at a fixed frequency during Nap or Sleep. Recovery time from Nap mode will increase if the clock is stopped, since the internal DLL can take up to 52s to regain lock at 250MSPS. By default after the device is powered on, the nap and sleep state is controlled by the NAPSLP pin as shown in Table 3.
NAPSLP Pin
AVSS Float AVDD
Power Dissipation
The power dissipated by the KAD5612P is primarily dependent on the sample rate, but is also related to the input signal in CMOS output mode. There is a static bias in the analog supply, while the remaining power dissipation is linearly related to the sample rate. The output supply dissipation is approximately constant in LVDS mode, but linearly related to the clock frequency in CMOS mode. Figures 35 and 36 illustrate these relationships.
Mode
Normal Sleep Nap
Table 3. NAPSLP Pin Settings Rev 0.5.1 Preliminary Page 17
KAD5612P
The power down mode can also be controlled through the SPI port, which overrides the NAPSLP pin setting. Details on this are contained in the Serial Peripheral Interface section. This is an indexed function when controlled from the SPI, but a global function when driven from the pin.
Data Format
Output data can be presented in three formats: two's complement, Gray code and offset binary. The data format is selected via the OUTFMT pin as shown in Table 4.
OUTFMT Pin
AVSS Float AVDD
Mode
Offset Binary Two's Complement Gray Code
Table 4. OUTFMT Pin Settings The data format can also be controlled through the SPI port, which overrides the OUTFMT pin setting. Details on this are contained in the Serial Peripheral Interface section. Offset binary coding maps the most negative input voltage to code 0x000 (all zeros) and the most positive input to 0xFFF (all ones). Two's complement coding simply complements the MSB of the offset binary representation. When calculating Gray code the MSB is unchanged. The remaining bits are computed as the XOR of the current bit position and the next most significant bit. Figure 37 shows this operation.
Figure 38. Gray Code to Binary Conversion Mapping of the input voltage to the various data formats is shown in Table 5.
Input Voltage
-Full Scale -Full Scale + 1LSB Mid-Scale +Full Scale - 1LSB +Full Scale
Offset Binary
000000000000 000000000001 100000000000 111111111110 111111111111
Two's Complement
100000000000 100000000001 000000000000 011111111110 011111111111
Gray Code
000000000000 000000000001 110000000000 100000000001 100000000000
Table 5. Input Voltage to Output Code Mapping
Serial Peripheral Interface
A serial peripheral interface (SPI) bus is used to facilitate configuration of the device and to optimize performance. The SPI bus consists of chip select (CSB), serial clock (SCLK) and serial data input/output (SDIO). The maximum SCLK rate is equal to the ADC sample rate (fSAMPLE) divided by 16 for write operations and fSAMPLE divided by 66 for reads. At fSAMPLE = 250MHz, maximum SCLK is 15.63MHz for writing and 3.79MHz for write operations. There is no minimum SCLK rate. The following sections describe various registers that are used to configure the SPI or adjust performance Rev 0.5.1 Preliminary Page 18
Figure 37. Binary to Gray Code Conversion Converting back to offset binary from gray code must be done recursively, using the result of each bit for the next lower bit as shown in Figure 38.
KAD5612P
or functional parameters. Many registers in the available address space (0x00 to 0xFF) are not defined in this document. Additionally, within a defined register there may be certain bits or bit combinations that are reserved. Undefined registers and undefined values within defined registers are reserved and should not be selected. Setting any reserved register or value may produce indeterminate results. mand. Data can be presented in MSB-first order or LSB-first order. The default is MSB-first, but this can be changed by setting 0x00[6] high. Figures 39 and 40 show the appropriate bit ordering for the MSB-first and LSB-first modes, respectively. In MSB-first mode the address is incremented for multi-byte transfers, while in LSB-first mode it's decremented. In the default mode the MSB is R/W, which determines if the data is to be read (active high) or written. The next two bits, W1 and W0, determine the number of data bytes to be read or written (see Table 6). The lower 13 bits contain the first address for the data transfer. This relationship is illustrated in Figure 41, and timing values are given in the Switching Specifications section. After the instruction/address bytes have been read, the appropriate number of data bytes are written to or read from the ADC (based on the R/W bit status). The data transfer will continue as long as CSB remains low and SCLK is active. Stalling of the CSB pin is allowed at any byte boundary (instruction/address or data) if the number of bytes being transferred is three or less. For transfers of four bytes or more, CSB is allowed stall in the middle of the instruction/address bytes or before the first data byte. If CSB transitions to a high state after that point the state machine will reset and terminate the data transfer.
SPI Physical Interface
The SPI port operates in a half or full duplex master/slave configuration, with the KAD5612P functioning as a slave. Multiple slave devices can interface to a single master. The chip-select bar (CSB) pin determines when a slave device is being addressed. Multiple slave devices can be written to concurrently, but only one slave device can be read from at a given time. If multiple slave devices are selected for reading at the same time, the results will be indeterminate. The serial clock pin (SCLK) provides synchronization for the data transfer. By default, all data is presented on the serial data input/output (SDIO) pin. The state of the SDIO pin is set automatically in the communication protocol (described below). A dedicated serial data output pin (SDO) can be activated by setting 0x00[7] high to allow operation in full duplex mode. The communication protocol begins with an instruction/address phase. The first rising SCLK edge following a high to low transition on CSB determines the beginning of the two-byte instruction/address com-
Figure 39. MSB-First Addressing
Figure 40. LSB-First Addressing Rev 0.5.1 Preliminary Page 19
KAD5612P
[W1:W0]
00 01 10 11
Bytes Transferred
1 2 3 4 or more
or LSB to MSB (LSB first) to accommodate various microcontrollers. Bit 7 Bit 6 SDO Active LSB First Setting this bit high configures the SPI to interpret serial data as arriving in LSB to MSB order. Bit 5 Soft Reset Setting this bit high resets all SPI registers to default values. Bit 4 Reserved This bit should always be set high. Bits 3:0 These bits should always mirror bits 4:7 to avoid ambiguity in bit ordering.
Table 6. Byte Transfer Selection Figures 42 and 43 illustrate the timing relationships for 2-byte and N-byte transfers, respectively. The operation for a 3-byte transfer can be inferred from these diagrams.
SPI Configuration
Address 0x00: chip_port_config Bit ordering and SPI reset are controlled by this register. Bit order can be selected as MSB to LSB (MSB first)
Figure 41. Instruction/Address Phase
Figure 42. 2-Byte Transfer
Figure 43. N-Byte Transfer Rev 0.5.1 Preliminary Page 20
KAD5612P
Address 0x02: burst_end If a series of sequential registers are to be set, burst mode can improve throughput by eliminating redundant addressing. In 3-wire SPI mode the burst is ended by pulling the CSB pin high. If the device is operated in 2-wire mode the CSB pin is not available. In that case, setting the burst_end address determines the end of the transfer. During a write operation, the user must be cautious to transmit the correct number of bytes based on the starting and ending addresses. Bits 7:0 Burst End Address This register value determines the ending address of the burst data.
Parameter 0x20[7:0] Coarse Offset
Steps -Full Scale (0x80) Mid-Scale (0x00) +Full Scale (0x7F) Nominal Step Size 256 -24.0mV 0.0mV +23.8mV 187.5V
0x21[7:0] Fine Offset
256 -1.7mV 0.0mV +1.7mV 13.3V
Table 7. Offset Adjustments Address 0x22: gain_coarse Address 0x23: gain_medium Address 0x24: gain_fine Gain of each ADC core can be adjusted in coarse, medium and fine steps. Coarse gain is a 4-bit adjustment while medium and fine are 8-bit. The data format is twos complement for all three registers. The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register.
Parameter
Steps -Full Scale (0x08) Mid-Scale (0x00) +Full Scale (0x07) Nominal Step Size
DUT Information
Address 0x08: chip_id Address 0x09: chip_version The generic die identifier and a revision number, respectively, can be read from these two registers.
Indexed DUT Configuration/Control
Address 0x10: device_index_A A common SPI map, which can accommodate single-channel or multi-channel devices, is used for all Kenet ADC products. Certain configuration commands (identified as Indexed in the SPI map) can be executed on a per-converter basis. This register determines which converter is being addressed for an Indexed command. It is important to note that only a single converter can be addressed at a time. This register defaults to 00h, indicating that no ADC is addressed. Address 0x20: offset_coarse Address 0x21: offset_fine The input offset of each ADC core can be adjusted in fine and coarse steps. Both adjustments are made via an 8-bit word as detailed in Table 7. The data format is twos complement. The default value of each register will be the result of the self-calibration after initial power-up. If a register is to be incremented or decremented, the user should first read the register value then write the incremented or decremented value back to the same register.
0x22[3:0] Coarse Gain
16 -11.2% 0.0% +9.8% 1.4%
Table 8. Coarse Gain Adjustment
Parameter
Steps -Full Scale (0x80) Mid-Scale (0x00) +Full Scale (0x7F) Nominal Step Size
0x23[7:0] Medium Gain
256 -10.56% 0.0% +10.48% 0.0825%
0x24[7:0] Fine Gain
256 -1.06% 0.0% +1.05% 0.00825%
Table 9. Medium and Fine Gain Adjustments Address 0x25: modes Two distinct reduced power modes can be selected. By default, the tri-level NAPSLP pin can select normal Rev 0.5.1 Preliminary Page 21
KAD5612P
operation, nap or sleep modes (refer to Nap/Sleep section). This functionality can be overridden and controlled through the SPI. This is an indexed function when controlled from the SPI, but a global function when driven from the pin. This register is not changed by a Soft Reset.
Value
000 001 010 100
0x25[2:0] Power Down Mode
Pin Control Normal Operation Nap Mode Sleep Mode
Figure 44. Phase Slip Address 0x72: clock_divide The KAD5612P has a selectable clock divider that can be set to divide by four, two or one (no division). By default, the tri-level CLKDIV pin selects the divisor (refer to Clock Input section). This functionality can be overridden and controlled through the SPI, as shown in Table 12. This register is not changed by a Soft Reset.
Value
000 001 010 100
Table 10. Power Down Control
Global DUT Configuration/Control
Address 0x70: skew_diff The value in the skew_diff register adjusts the timing skew between the two ADCs cores. The nominal range and resolution of this adjustment are given in Table 11. The default value of this register after power-up is 00h.
Parameter
Steps -Full Scale (0x08) Mid-Scale (0x00) +Full Scale (0x07) Nominal Step Size
0x72[2:0] Clock Divider
Pin Control Divide by 1 Divide by 2 Divide by 4
0x70[7:0] Differential Skew
256 -6.5ps 0.0ps +6.5ps 51fs
Table 12. Clock Divider Selection Address 0x73: output_mode_A The output_mode_A register controls the physical output format of the data, as well as the logical coding. The KAD5612P can present output data in two physical formats: LVDS or LVCMOS. Additionally, the drive strength in LVDS mode can be set high (3mA) or low (2mA). By default, the tri-level OUTMODE pin selects the mode and drive level (refer to Digital Outputs section). This functionality can be overridden and controlled through the SPI, as shown in Table 13. Data can be coded in three possible formats: two's complement, Gray code or offset binary. By default, the tri-level OUTFMT pin selects the data format (refer to Data Format section). This functionality can be overridden and controlled through the SPI, as shown in Table 14. This register is not changed by a Soft Reset.
Table 11. Differential Skew Adjustment Address 0x71: phase_slip When using a clock divider, it's not possible to determine the synchronization of the incoming and divided clock phases. This is particularly important when multiple ADCs are used in a time-interleaved system. The phase slip feature allows the rising edge of the divided clock to be advanced by one input clock cycle, as shown in Figure 44.
Rev 0.5.1 Preliminary
Page 22
KAD5612P
Value
000 001 010 100
0x93[7:5] Output Mode
Pin Control LVDS 2mA LVDS 3mA LVCMOS
ing. A static word can be placed on the output bus, or two different words can alternate. In the alternate mode, Address 0xC0: test_io Bits 7:6 User Test Mode These bits set the test mode to static (0x00) or alternate (0x01) mode. Other values are reserved. The four LSBs in this register (Output Test Mode) determine the test pattern in combination with registers 0xC2 through 0xC5. Refer to Table 15.
Value
0000 0001 0010 0011 0100 0101 0110 0111 1000
Table 13. Output Mode Control
Value
000 001 010 100
0x93[2:0] Output Format
Pin Control Two's Complement Gray Code Offset Binary
0xC0[3:0] Output Test Mode
Off Midscale Positive Full-Scale Negative Full-Scale Checkerboard Reserved Reserved One/Zero User Pattern
Word 1
Word 2
0x8000 0xFFFF 0x0000 0xAAAA N/A N/A 0xFFFF user_patt1
N/A N/A N/A 0x5555 N/A N/A 0x0000 user_patt2
Table 14. Output Format Control Address 0x74: output_mode_B Address 0x75: config_status Bit 6 DLL Range This bit sets the DLL operating range to fast (TBD2MSPS to 250MSPS) or slow (40 to TBD1MSPS). Bit 4 DDR Enable Setting this bit enables Double Data-Rate mode. The output_mode_B and config_status registers are used in conjunction to enable DDR mode and select the frequency range of the DLL clock generator. The method of setting these options is different from the other registers.
Table 15. Output Test Modes Address 0xC2: user_patt1_lsb Address 0xC3: user_patt1_msb These registers define the lower and upper eight bits, respectively, of the first user-defined test word. Address 0xC2: user_patt2_lsb Address 0xC3: user_patt2_msb These registers define the lower and upper eight bits, respectively, of the second user-defined test word.
Figure 45. Setting output_mode_B register The procedure for setting output_mode_B is shown in Figure 45. Read the contents of output_mode_B and config_status and XOR them. Then XOR this result with the desired value for output_mode_B and write that XOR result to the register.
DUT Test
The KAD5612 can produce preset or user defined patterns on the digital outputs to facilitate in-situ testRev 0.5.1 Preliminary Page 23
KAD5612P
SPI Memory Map
Addr (Hex) 00 01 02 03-07 08 09 10 11-1F 20 21 22 23 24 25 DUT SPI Config Info Parameter Name port_config reserved burst_end reserved chip_id chip_version device_index_A reserved offset_coarse offset_fine gain_coarse gain_medium gain_fine modes Bit 7 (MSB) Bit 6 Bit 5 Soft Reset Reserved Burst end address [7:0] Reserved Chip ID # Chip Version # Reserved Reserved Coarse Offset Fine Offset Reserved Medium Gain Fine Gain Bit 4 Bit 3 Bit 2 Mirror (bit5) Bit 1 Mirror (bit6) Bit 0 (LSB) Mirror (bit7) Def. Value Indexed/ (Hex) Global 00h 00h Read only Read only 00h cal. value cal. value cal. value cal. value cal. value 00h NOT affected by Soft Reset G G G G I I I I I I I SDO Active LSB First
ADC01
ADC00
Indexed DUT Config/Control
Coarse Gain
Power Down Mode [2:0] 000=Pin Control 001=Normal Operation 010=Nap 100=Sleep other codes=reserved
26-5F 60-6F 70 71 72
reserved reserved skew_diff phase_slip clock_divide
Reserved Reserved Differential Skew Reserved Clock Divide [2:0] 000=Pin Control 001=divide by 1 010=divide by 2 100=divide by 4 other codes=reserved Output Format [2:0] 000=Pin Control 001=Twos Complement 010=Gray Code 100=Offset Binary other codes=reserved DDR Enable Next Clock Edge 7Fh 00h 00h NOT affected by Soft Reset 00h NOT affected by Soft Reset 00h NOT affected by Soft Reset Read Only Output Test Mode [3:0] 7=One/Zero Word Toggle 8=User Input 9-15=reserved 00h G G G
Global DUT Config/Control
73
output_mode_A
74
output_mode_B
Output Mode [2:0] 000=Pin Control 001=LVDS 2mA 010=LVDS 3mA 100=LVCMOS other codes=reserved DLL Range 0=fast 1=slow
G
G
75 76-BF C0
config_status reserved test_io
XOR Result User Test Mode [2:0] 00=Single 01=Alternate 10=Single Once 11=Alternate Once Reset PN Long Gen
XOR Result Reserved Reset PN Short Gen 0=Off
G G
DUT Test
1=Midscale Short 2=+FS Short 3=-FS Short 4=Checker Board 5=reserved 6=reserved B5 B13 B5 B13 B4 B12 B4 B12 Reserved B3 B11 B3 B11 Reserved B2 B10 B2 B10
C1 C2 C3 C4 C5 C6-FF
Reserved user_patt1_lsb user_patt1_msb user_patt2_lsb user_patt2_msb reserved
B7 B15 B7 B15
B6 B14 B6 B14
B1 B9 B1 B9
B0 B8 B0 B8
00h 00h 00h 00h 00h
G G G G G
Table 16. SPI Memory Map
Rev 0.5.1 Preliminary
Page 24
KAD5612P
Equivalent Circuits
Figure 46. Analog Inputs
AVDD
Figure 50. LVDS Outputs
AVDD
To Charge Pipeline AVDD 11k 18k
CLKP
Figure 51. CMOS Outputs
AVDD
11k
18k
CLKN
Figure 52. VCM_OUT Output Figure 47. Clock Inputs
Layout Considerations
Split Ground and Power Planes
Data converters operating at high sampling frequencies require extra care in PC board layout. Many complex board designs benefit from isolating the analog and digital sections. Analog supply and ground planes should be laid out under signal and clock inputs. Locate the digital planes under outputs and logic pins. Grounds should be joined under the chip.
Figure 48. Tri-Level Digital Inputs
Clock Input Considerations
Use matched transmission lines to the transformer inputs for the analog input and clock signals. Locate transformers and terminations as close to the chip as possible. Figure 49. Digital Inputs Rev 0.5.1 Preliminary Page 25
KAD5612P
Exposed Paddle
The exposed paddle must be electrically connected to analog ground (AVSS) and should be connected to a large copper plane using numerous vias for optimal thermal performance. Clock Duty Cycle is the ratio of the time the clock wave is at logic high to the total time of one clock period. Differential Non-Linearity (DNL) is the deviation of any code width from an ideal 1 LSB step. Effective Number of Bits (ENOB) is an alternate method of specifying Signal to Noise-and-Distortion Ratio (SINAD). In dB, it is calculated as: ENOB = (SINAD-1.76) / 6.02 Gain Error is the ratio of the difference between the voltages that cause the lowest and highest code transitions to the full-scale voltage (less 2 LSB). It is typically expressed in percent. Integral Non-Linearity (INL) is the deviation of each individual code from a line drawn from negative fullscale (1/2 LSB below the first code transition) through positive full-scale (1/2 LSB above the last code transition). The deviation of any given code from this line is measured from the center of that code. Least Significant Bit (LSB) is the bit that has the smallest value or weight in a digital word. Its value in terms of input voltage is VFS/(2N-1) where N is the resolution in bits. Missing Codes are output codes that are skipped and will never appear at the ADC output. These codes cannot be reached with any input value. Most Significant Bit (MSB) is the bit that has the largest value or weight. Pipeline Delay is the number of clock cycles between the initiation of a conversion and the appearance at the output pins of the data. Power Supply Rejection Ratio (PSRR) is the ratio of a change in input voltage necessary to correct a change in output code that results from a change in power supply voltage. Signal to Noise-and-Distortion (SINAD) is the ratio of the RMS signal amplitude to the RMS value of the sum of all other spectral components below one half the clock frequency, including harmonics but excluding DC. Signal-to-Noise Ratio (without Harmonics) is the ratio of the RMS signal amplitude to the sum of all other spectral components below one-half the sampling frequency, excluding harmonics and DC. SNR and SINAD are either given in units of dBc (dB to carrier) when the absolute power of the fundamental is used as the reference, or dBFS (dB to full scale) when the converter's full-scale input power is used as the reference.
Bypass and Filtering
Bulk capacitors should have low equivalent series resistance. Tantalum is a good choice. For best performance, keep ceramic bypass capacitors very close to device pins. Longer traces will increase inductance, resulting in diminished dynamic performance and accuracy. Make sure that connections to ground are direct and low impedance. Avoid forming ground loops.
LVDS Outputs
Output traces and connections must be designed for 50 (100 differential) characteristic impedance. Keep traces direct and minimize bends where possible. Avoid crossing ground and power plane breaks with signal traces.
LVCMOS Outputs
Output traces and connections must be designed for 50 characteristic impedance.
Unused Inputs
Standard logic inputs (RESETN, CSB, SCLK, SDIO, SDO) which will not be operated do not require connection to ensure optimal ADC performance. These inputs can be left floating if they are not used. Tri-level inputs (NAPSLP, OUTMODE, OUTFMT, CLKDIV) accept a floating input as a valid state, and therefore should be biased according to the desired functionality.
Definitions
Analog Input Bandwidth is the analog input frequency at which the spectral output power at the fundamental frequency (as determined by FFT analysis) is reduced by 3dB from its full-scale low-frequency value. This is also referred to as Full Power Bandwidth. Aperture Delay or Sampling Delay is the time required after the rise of the clock input for the sampling switch to open, at which time the signal is held for conversion. Aperture Jitter is the RMS variation in aperture delay for a set of samples. Rev 0.5.1 Preliminary
Page 26
KAD5612P
Spurious-Free-Dynamic Range (SFDR) is the ratio of the RMS signal amplitude to the RMS value of the peak spurious spectral component. The peak spurious spectral component may or may not be a harmonic. Two-Tone SFDR is the ratio of the RMS value of the lowest power input tone to the RMS value of the peak spurious component, which may or may not be an IMD product.
Outline Dimensions
Figure 53. 72QFN Dimensions Rev 0.5.1 Preliminary Page 27
KAD5612P
Ordering Guide
RoHS
The KAD5612P is compliant with EU directive 2002/95/EC regarding the Restriction of Hazardous Substances (RoHS). Contact Kenet for a materials declaration for this product.
Model
KAD5612P-25Q72 KAD5612P-21Q72 KAD5612P-17Q72 KAD5612P-12Q72
Speed
250MSPS 210MSPS 170MSPS 125MSPS
Package
72-QFN 72-QFN 72-QFN 72-QFN
Temp. Range
-40C to +85C -40C to +85C -40C to +85C -40C to +85C
Revision History
14-May-07: 21-Jun-07: 13-Aug-07: 07-Dec-07: 21-Feb-08: 25-Feb-08: Rev 0.1 Rev 0.2 Rev 0.3 Rev 0.4 Rev 0.5 Rev 0.5.1 Updated to new format Errata Updated Content/specification updates Content/specification updates New Pinout, Updated specifications, added functional descriptions Added skew_diff SPI register description (p. 22)
Preliminary Datasheet
This datasheet contains preliminary technical data, which is subject to change without notice. Contact Kenet prior to initiating design activity using this product.
Rev 0.5.1 Preliminary
Page 28

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